1. Field
Exemplary embodiments of the present invention relate to a memory chip and a semiconductor package including a plurality of memory chips.
2. Description of the Related Art
According to the recent trend, the capacity and speed of a semiconductor memory used as a memory device in most electronic systems have been increasing. Furthermore, various attempts have been made to mount a memory with a larger capacity in a smaller area and to effectively drive the memory.
In order to increase the integration degree of a memory, a three-dimensional (3D) structure including a plurality of memory chips stacked therein started to be applied instead of an existing two-dimensional (2D) structure. As memories with a high integration degree and a high capacity are needed, a 3D stacked structure of a memory chip may be used to increase a capacity and reduce a semiconductor chip size, thereby improving an integration degree.
As the 3D stacked structure, a through-silicon via (TSV) structure may be applied. The TSV structure is considered as an alternative for overcoming the reduction of transmission speed depending on a distance from a controller on a module, the vulnerability of data bandwidth, and the degradation of transmission speed depending on variables on a package. The TSV structure includes a path formed through a plurality of memory chips and an electrode formed in the path to perform communication between the stacked chips.